Stable clock generation internal to a functional integrated circuit chip

ABSTRACT

Methods and apparatus that provide stable clock generation within a functional integrated circuit are disclosed. The functional integrated circuit provides a function other than clock generation, such as a peripheral or interrupt control. Typically, the clock generation is phase-lock loop (PLL) based. The functional integrated circuit also typically provides power savings modes to conserve power consumption.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application Ser.No. 60/144,271, filed Jul. 15, 1999, and entitled “STABLE CLOCKGENERATION INTERNAL TO A FUNCTIONAL INTEGRATED CIRCUIT CHIP”, thecontent of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to clock generation and, moreparticularly, to stable clock generation internal to a functionalintegrated circuit chip.

2. Description of the Related Art

Conventionally, clock generator chips have been separate integratedcircuit chips provided to produce clocks of varying frequencies for useby other parts, namely, other integrated circuit chips, of an electricalcircuit design. As an example, it is common for a computer system toinclude a separate clock generator chip to produce the various clocks ofdifferent frequencies used by the other circuitry within the computersystem. Generally speaking, a clock generator chip will receive an inputclock and produce a series of output clocks, each having a differentfrequency. The output clocks can have frequencies greater than or lessthan the frequency of the input clock.

FIG. 1 is a block diagram of a representative conventional clockgenerator chip 100. The clock generator chip 100 includes a multiplier102 that receives an input clock. The multiplier 102 multiplies theinput clock to a greater frequency and supplies the resulting clock to aseries of dividers. Specifically, the clock generator chip 100 includesa divider 104 and a phase-lock loop (PLL) 106 which together produce afirst clock signal (CLK1). The divider 104 receives the resulting clockfrom the multiplier 102 and supplies it to the PLL 106 which outputs thefirst clock (CLK1). The clock generator chip 100 also includes a divider108 and a PLL 110 that produce a second clock (CLK2) in a similarmanner. Further, the clock generator chip 100 includes a divider 112 anda PLL 114 that together produce a third clock (CLK3) also in a similarmanner.

When the conventional clock generator chip 100 together with an externalclock generator that produces the input clock are powered-on, the clockgenerator chip 100 is normally held in reset until the input clock hasstabilized and propagated through the clock generator chip. Thereafter,the clock generator chip 100 can be released from reset such that theoutput clocks are able to be produced in a stable manner.

However, more recently, with the ever-increasing integration offunctionality onto integrated circuit chips, the clock generatorcircuitry, including the PLLs, has been moved inside a functional chip.In such situations, there arise stability problems, or unstableconditions, which prevent the reliable generation of the desired clocksignals. These unstable conditions can cause the PLLs to incorrectlylock to an unstable external clock if the external clock is powered-upbefore the functional chip is powered-up. Here, the external clock mightnot be able to stabilize with the functional chip being powered-off.Hence, when the functional chip is subsequently powered-up, the PLLswithin the functional chip may incorrectly lock to the unstable externalclock source. Also, if an input to the functional chip is driven whilethe functional chip is powered down, then the functional chip mayexperience destructive latch-up when it is subsequently powered up.Still further, if the external clock and the functional chip arepowered-up at the same time but the PLLs within the functional chip aredisabled while the chip is held in reset, no clocks are propagatedthrough the logic of the functional chip held in reset, so thefunctional chip will not be properly reset. Also, when the PLLs areeventually enabled, they will drive the functional chip with theunstable clocks until the internal PLLs stabilize.

Thus, there is a need to provide improved techniques for powering onfunctional chips which include PLL-based clock generation circuitry.

SUMMARY OF THE INVENTION

Broadly speaking, the invention relates to stable clock generationwithin a functional integrated circuit. The functional integratedcircuit provides a function other than clock generation, such asperipheral or interrupt control. Typically, the clock generation isphase-lock loop (PLL) based. The functional integrated circuit alsotypically provides power savings modes to conserve power consumption.

The invention can be implemented in numerous ways, including as asystem, a device, an apparatus, and a method. Several embodiments of theinvention are summarized below.

As an integrated circuit chip having internal functional circuitry, withthe integrated circuit chip receiving an external clock, a reset signaland a clock stop signal, one embodiment of the invention includes: aclock control circuit that receives the reset signal and the clock stopsignal and produces a clock control signal; a phase lock loop circuitthat receives the external clock and produces a generated clock based onthe external clock; a multiplexer that receives the external clock andthe generated clock, and outputs at an output terminal one of theexternal clock and the generated clock as a selected clock based on theclock control signal; and a clock stopper to permit or block passage ofthe selected clock to the internal functional circuitry of theintegrated circuit chip.

As a controller integrated circuit chip for providing control functionsfor a computer system, one embodiment of the invention includes anon-board clock generation circuit that produces a plurality of clocks,and functional controller circuitry that operates using the plurality ofclocks. The on-board clock generation circuit includes at least: a phaselock loop circuit that receives the external clock and produces agenerated clock based on the external clock; a multiplexer that receivesthe external clock and the generated clock, and outputs one of theexternal clock and the generated clock as a selected clock; and a clockstopper that operates to permit or block passage of the selected clockto the functional controller circuitry of the controller integratedcircuit chip.

As a controller integrated circuit chip for providing control functionsfor a computer system, another embodiment of the invention includes anonboard clock generation circuit that produces a plurality of clocks,and functional controller circuitry that operates using the plurality ofclocks. The on-board clock generation circuit includes at least: a phaselock loop circuit that receives the external clock and produces agenerated clock based on the external clock; a clock stopper thatoperates to permit or block passage of either the external clock or thegenerated clock to the functional controller circuitry of the controllerintegrated circuit chip. The on-board clock generation circuit alsohaving a run mode and a low-power mode, in the run mode the internalclock is supplied to the functional controller circuitry, and in thelow-power mode the clock stopper prevents either the external clock orthe generated clock from being supplied to the functional controllercircuitry.

As a computer system, one embodiment of the invention includes: a memorydevice that stores computer code; a microprocessor chip that executesthe computer code; a peripheral bus; and a controller chip for theperipheral bus. The controller chip includes an on-board clockgeneration circuit that produces a plurality of clocks, and functionalcontroller circuitry that operates using the plurality of clocks tocontrol interaction with the peripheral bus. Further, the on-board clockgeneration circuit includes at least: a phase lock loop circuit thatreceives the external clock and produces a generated clock based on theexternal clock; a multiplexer that receives the external clock and thegenerated clock, and outputs one of the external clock and the generatedclock as a selected clock; and a clock stopper that operates to permitor block passage of the selected clock to the functional controllercircuitry of the controller chip.

As a method for powering up an integrated circuit chip having functionalcircuitry and internal clock generation circuitry including phase-lockedloops (PLLs) to produce internal clocks, one embodiment of the inventionincludes the acts of: providing power to the integrated circuit chip andto an external clock source but not providing power to the PLLs;bypassing the PLLs to produce an externally generated clock, theexternally generated clock being provided by the external clock source;permitting the externally generated clock to be supplied to thefunctional circuitry, thereby allowing processing of a reset operationwhile the PLLs are not producing the internal clocks; subsequentlystopping the externally generated clock from being supplied to thefunctional circuitry after the reset operation is processed; providingpower to the PLLs; unbypassing the PLLs after their output are stable;and thereafter permitting the internal clocks produced by the PLLs to besupplied to the functional circuitry, so as to operate the functionalcircuitry in a normal manner.

The advantages of the invention are numerous. Different embodiments orimplementations may have one or more of the following advantages. Oneadvantage of the invention is that stable clock generation with powermanagement can be performed internal to a functional integrated circuit.Another advantage of the invention is that functional integratedcircuits are able to be properly reset upon being initially powered-up.Yet another advantage of the invention is that phase-lock loops (PLLs)used in the clock generation lock to desired frequencies in a stablemanner. Still another advantage of the invention is that PLLs and clockscan be started and stopped cleanly and in the proper sequence, withouthaving to reset the logic associated with those clocks, for powermanagement.

Other aspects and advantages of the invention will become apparent fromthe following detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings,wherein like reference numerals designate like structural elements, andin which:

FIG. 1 is a block diagram of a representative conventional clockgenerator chip;

FIG. 2A is a block diagram of a portion of a computer system accordingto one embodiment of the invention;

FIG. 2B is a schematic diagram of a clock start/stop circuit;

FIG. 3A is a schematic diagram of a control circuit according to oneembodiment of the invention.

FIG. 3B is a block diagram of a controller chip according to anotherembodiment of the invention;

FIG. 4 is a flow diagram of power down processing according to oneembodiment of the invention;

FIGS. 5A-5D pertain to power up processing for a controller chipaccording to one embodiment of the invention;

FIG. 6 is a flow diagram of sleep processing according to one embodimentof the invention; and

FIG. 7 is a flow diagram of awaken processing according to oneembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to stable clock generation within a functionalintegrated circuit. The functional integrated circuit provides afunction other than clock generation, such as a controller operation.Typically, the clock generation is phase-lock loop (PLL) based. Thefunctional integrated circuit also typically provides power savingsmodes to conserve power consumption.

Embodiments of the invention are discussed below with reference to FIGS.2A-7. However, those skilled in the art will readily appreciate that thedetailed description given herein with respect to these figures is forexplanatory purposes as the invention extends beyond these limitedembodiments. The invention is primarily discussed below with referenceto input/output (I/O) controller chip; however, it should be understoodthat the invention is generally applicable to any type of functionalintegrated circuit (functional chip) that desires clock generation.

FIG. 2A is a block diagram of a portion of a computer system 200according to one embodiment of the invention. The computer system 200,among other things, includes an input/output (I/O) controller chip 202,an oscillator 204, and a power manager 206. The I/O controller chip 202represents a functional integrated circuit chip that includes clockgeneration circuitry as well as functional circuitry. The portion of theI/O controller chip 202 illustrated in FIG. 2A pertains to the clockgeneration circuitry. The functional circuitry that would be associatedwith the I/O controller chip is conventional and well known in the artand thus not shown herein. Also, the computer system 200 includesvarious other integrated circuit chips (e.g., memory, microprocessor,bus, etc.) that are conventional and well known in the art, and thus notshown in FIG. 2A. Typically, the power manager 206 controls powermanagement of various other integrated circuits within the computersystem 200 besides the I/O controller chip 202.

In any case, the clock generation circuitry within the I/O controllerchip 202 includes a phase-lock loop (PLL) 208 that receives an inputclock from the oscillator 204. The oscillator 204 can be considered anexternal clock generator for the I/O controller chip 202 and thus theinput clock can be considered an external clock. The input clockproduced by the oscillator 204 is supplied to the PLL 208. The PLL 208is configured to output a clock signal at a particular frequency. Inoperation, the PLL 208 locks its output frequency to a predeterminedfrequency. Often, the predetermined frequency is greater than thefrequency of the input clock. Although not shown in FIG. 2A, the PLL 208can also perform multiplication and division operations so as to yieldthe predetermined frequency, such as conventionally done with themultiplier 102 and dividers 104, 108 and 112 shown in FIG. 1. Thesemultipliers and dividers, if any, can be provided within the block 208shown in FIG. 2A.

The PLL 208 is unstable during its initial startup period when it isattempting to stabilize so as to produce the predetermined frequency.Once stabilized, the output frequency PLL 208 is deemed locked. Theoutput clock from the PLL 208 is supplied to a multiplexer 210. Themultiplexer 210 also receives the input clock supplied by the oscillator204 . The input clock being supplied to the multiplexer 210 is alsoreferred to herein as a bypass clock (or a reset clock) because itserves to bypass the PLL 208. The output clock produced by the PLL 208is also referred to as a run clock (or a normal clock) because it servesas the normal, running clock for the I/O controller chip 202 whenoperational. The multiplexer 210 operates to select one of the run clockand the bypass clock to be output as a selected clock. The selectedclock from the multiplexer 210 is then supplied to a clock stopper 212.The clock stopper 212 is controlled to be either active or inactive.When inactive, the clock stopper 212 passes the selected clock throughthe clock stopper 212 and thus supplies an internal clock to thefunctional circuitry of the I/O controller chip 202. On the other hand,when the clock stopper 212 is activated, the clock stopper 212 preventsthe selected clock from being supplied to the functional circuitry. TheI/O controller chip 202 can produce other internal clocks using similarcircuitry. In particular, the I/O controller chip 202 also includes aPLL 214, a multiplexer 216 and a clock stopper 218 that together produceanother internal clock of a different frequency for the functionalcircuitry within the I/O controller chip 202. Often, the I/O controllerchip 202 will produce a series of internal clocks with differentfrequencies as different parts of the functionality circuitry require aclock with a particular frequency. For example, in one embodiment, theinput clock is 18.432 MHz and seven (7) internal clocks with frequenciesof 15.6672, 19.5840, 31.3344, 32.000, 45.1584, 48.000 and 49.1520 MHzare respectively produced. The clock stoppers 212 and 218 operate tooutput the internal clocks cleanly when starting and stopping (i.e., theinternal clocks do not contain spikes or short clock segments).

According to the invention, to provide stable power-on for the I/Ocontroller chip 202, the power manager 206 provides an I/O clock stopsignal (I/O CLK STOP) and a reset signal (RESET) to the I/O controllerchip 202. As noted by bar over these signal names, the I/O clock stopsignal (I/O CLK STOP) and a reset signal (RESET) are active low in thisembodiment, Together, these signals from the power manager 206 providethe I/O controller chip 202 with enough control information to not onlyplace the I/O controller chip 202 in a sleep or shutdown mode toconserve power, but also power-on the clock generation circuitry in amanner in which stable clocks will be produced. The control sequencingfor the I/O controller chip 202 during power-on as well as the sleep andshutdown modes is described below.

FIG. 2B is a schematic diagram of a clock stopper 250 suitable for useas the clock stoppers 212 and 218 of FIG. 2A. The clock stopper 250 is acircuit that can cleanly start or stop a clock from being output. Theclock stopper 250 includes a first flip-flop circuit 252, a secondflip-flop circuit 254, and a logical OR gate 256. In this embodiment,the first and second flip-flops 252 and 254 are data-type flip-flops. Astop clock signal (STOP CLK) is received at a data terminal of the firstflip-flop 252. An input clock (CLKin) is received at a clock terminal ofthe first flip-flop 252 and the second flip-flop 254. An output terminalof the first flip-flop 252 connected to a data terminal of the secondflip-flop 254. An output terminal of the second flip-flop 254 connectsto one input terminal of the logical OR gate 256 and the input clock(CLKin) connects to the other input to the logical OR gate 256. Theoutput of the logical OR gate 256 is an output clock (CLKout). The clockstopper 250 operates to output the output clock (CLKout) without anyspikes or short clock segments following either a start or stopoperation.

FIG. 3A is a schematic diagram of a control circuit 300 according to oneembodiment of the invention. The control circuit 300 is suitable for usewithin the I/O controller chip 202 illustrated in FIG. 2A. The controlcircuit 300 receives the I/O clock stop signal and the reset signal fromthe power manager 206 and produces control signals (e.g., sleep, bypassand shutdown signals) that are used by the clock generation circuitry toensure that stable internal clocks are produced for the functionalcircuitry within the I/O controller chip 202.

The control circuit 300 includes a sleep state bit register 302 andinverters 304 and 306. The sleep state bit register 302 produces a sleepsignal. The I/O clock stop (I/O CLK STOP) signal is inverted by theinverter 304, and the reset (RESET) signal is inverted by the inverter306. The sleep state bit register 302 receives the inverted clock stopsignal at a set terminal of the sleep state bit register 302, andreceives an inverted reset signal at a clear terminal (CLR) of the sleepstate bit register 302. When the inverted clock stop signal is high(“1”), the sleep state is set in the sleep state bit register 302, andthus the sleep signal is high (“1”), thereby stopping the clockscleanly. When the inverted reset signal is high (“1”), the sleep stateis cleared in the sleep state bit register 302, and thus the sleepsignal is low (“0”), thereby allowing the clocks to run. A clearoperation overrides a set operation if both the inverted clock stopsignal and the inverted reset signal are high.

The inverted clock stop signal and the inverted reset signal aresupplied to an AND gate 308. The output of the AND gate 308 is suppliedto a clock terminal of a flip-flop 310. The data terminal (D) is pulledup to a high potential (“1”), and a clear terminal (CLR) is connected tothe inverted clock stop signal. The flip-flop 310 also has an outputterminal (Q) which outputs a bypass signal (BYPASS_PLL) that is suppliedto the multiplexers, such as the multiplexers 210 and 216 illustrated inFIG. 2A. Accordingly, the bypass signal is high (“I”) to request use ofthe bypass clock when the I/O clock stop signal and the reset signal areboth asserted (“low”) until the I/O clock stop signal is de-asserted(“high”). Typically, the bypass signal is supplied to a select terminalof the multiplexers to choose one of the input clocks to be the selectedclock.

In addition, since the clock generation circuitry of the I/O controllerchip 202 has a shut-down mode and a sleep mode in which the PLLs 208 and214 can be turned off to reduce power consumption, the control circuit300 includes an AND gate 312 that receives a first input from theinverted reset signal and a second input as the bypass signal.

Still further, the control circuit 300 can produce a signal that is usedto provide even more power savings by the I/O controller chip 202. Toprovide such a deeper shutdown, the control circuit 300 further includesan inverter 314, an AND gate 316, and an AND gate 318. The inverter 314inverts the bypass signal to produce an inverted bypass signal. The ANDgate 316 receives the inverted bypass signal as a first input andreceives the inverted clock stop signal as a second input. The output ofthe AND gate 316 is supplied to the AND gate 318 as a first input. Thesleep signal produced by the sleep state bit register 302 is supplied tothe AND gate 318 as a second input. A third input for the AND gate 318is a signal indicating that all of the internal clocks have been stopped(e.g., by clock stoppers) as a result of the sleep signal. For example,with respect to the I/O controller chip 202 illustrated in FIG. 2A, thesignal indicating that all the clocks have stopped would indicate thatthe clock stoppers 212 and 218 are both activated and thus preventinternal clocks from being supplied to the functional circuitry withinthe I/O controller chip 202. The output from the AND gate 318 is a totalshutdown signal (SHUTDOWN_PLL_TOTAL). As an example, the total shutdownsignal can operate to shutdown additional features of the I/O controllerchip 202 besides the PLLs. For example, with respect to the clockgeneration circuitry, such additional features can include inputcomparator circuits, other clocks being produced or received by the I/Ocontroller chip 202, etc.

Still further the control circuit 300 also includes an OR gate 320. Theoutput of the AND gate 312 is supplied to a first input of the OR gate320, and the total shutdown signal (SHUTDOWN_PLL_TOTAL) output from theAND gate 318 is supplied to a second input of the OR gate 320. Theoutput of the OR gate 320 is a PLL shutdown signal (SHUTDOWN_PLL) whichis supplied to the PLLs, such as the PLLs 208 and 214 illustrated inFIG. 2A. Normally, the shutdown signal disconnects the PLLs from power.

FIG. 3B is a block diagram of an I/O controller chip 350 according toanother embodiment of the invention. Although not shown in FIG. 3B, theI/O controller chip 350 typically includes clock control circuitry suchas the control circuit 300 shown in FIG. 3A.

The I/O controller chip 350 is similar to the I/O controller chip 202illustrated in FIG. 2A. Specifically, the I/O controller chip 350includes the circuitry 208-218 that produces first and second internalclocks (INTCLK1 and INTCLK2). In addition, to produce the first internalclock, the I/O controller chip 350 further includes an input comparator352 and a capacitor 354. The input comparator 352 receives a first inputclock (IC1) at a first input terminal and couples a second inputterminal to ground through the capacitor 354. The input comparator 352operates to remove common-mode noise from the first input clock (IC1).The circuitry 214-218 that produces the second internal clock (INTCLK2)also includes an input comparator 356 and a capacitor 358. The inputcomparator 356 receives a second input clock (IC2) at a first inputterminal and couples a second input terminal of the input comparator 356to ground through the capacitor 358. The input comparator 356 alsoremoves common-mode noise from the second input clock (IC2).

The I/O controller chip 350 can also support specialized clocks that areoften provided or utilized within computer systems. One such example ofa specialized clock is a PCI clock (PCICLK). The PCI clock is normallyrun at 33 MHz but could also run at 66 MHz if the normal clock is notyet available. Hence, the I/O controller chip 350 receives a third inputclock (IC3) at a first input terminal of an input comparator 360. Asecond input terminal of the input comparator 360 is coupled to groundthrough a capacitor 362. Here, the third input clock (IC3) has afrequency of 33 MHz. The input comparator 360 operates to reduce anycommon-mode noise that may be provided on the third input clock (IC3).The clock output by the input comparator 360 is supplied to a phase-lockloop (PLL) 364 which also includes a times-two (2×) multiplier. The PLL364 produces a 66 MHz clock by multiplying the third input clock by afactor of two (2). A multiplexer 368 receives the 33 MHz clock and the66 MHz clock and operates to select one of these clocks. The selectedclock is then directed through a clock stopper 370 and becomes the PCIclock (PCICLK). It should also be noted that the power to the inputcomparators 352, 356 and 360 can be separately controlled by hardware orsoftware to provide power savings, such as by power shut down when thesecomponents are not in use.

FIG. 4 is a flow diagram of power down processing 400 according to oneembodiment of the invention. The power down processing 400 is theprocessing performed to power down a controller chip, such as the I/Ocontroller chip 202 illustrated in FIG. 2A.

The power down processing 400 initially drives 402 the I/O clock stopsignal (I/O CLK STOP) low. Then, the reset signal (RESET) is driven 404low. In one embodiment, such as shown in FIG. 2A, the I/O clock stopsignal and the reset signal can be supplied to the I/O controller chip202 by a power manager, such as the power manager 206 illustrated inFIG. 2A. Accordingly, the power manager can determine when power downprocessing 400 should be performed. Alternatively, the power downprocessing 400 can also be driven or controlled by a state machineinternal to the chip controller.

In any event, after the reset signal is driven 404 low, the powersupplied to the controller chip and its external clock sources is turnedoff 406. For example, with respect to FIG. 2A, the power to the I/Ocontroller chip 202 and the oscillator 204 is turned off. After thepower is turned off, the power down processing 400 is complete and ends.

FIGS. 5A-5E pertain to power up processing for an I/O controller chipaccording to one embodiment of the invention. The power up processing isthe processing performed to power up a controller chip, such as the I/Ocontroller chip 202 illustrated in FIG. 2A. The power up processing ismore sophisticated than the power down processing because the sequenceof events and operations need to be controlled so that the internalclocks being produced by the clock generation circuitry are stable.

More particularly, FIG. 5A is a flow diagram of power up processing 500according to one embodiment of the invention. The power up processing500 initially drives 502 the I/O clock stop signal (I/O CLK STOP) andthe reset signal (RESET) low. Then, the controller chip and its externalclock sources are powered on 504. At this point, to allow the circuitrywithin the controller chip to process these signals, the power upprocessing delays 506 for a first predetermined duration. The firstpredetermined delay can vary widely with different implementations. Forexample, in one embodiment, the first predetermined duration is 10milliseconds, which is the time required for the external clocks tostabilize.

After the first predetermined duration, the reset signal is driven 508high. After the reset signal is driven 508 high, the power up processing500 delays 510 for a second predetermined duration. Again, the delay isutilized so that the circuitry within the controller chip can processthe signals (i.e., conform to the control conditions). The secondpredetermined delay can also vary widely with different implementations.For example, in one embodiment, the second predetermined delay is 250microseconds, which is the time required for the PLLs to lock andstabilize.

After the delay for the second predetermined duration, the I/O clockstop signal (I/O CLK STOP) is driven 512 high, the power up processing500 delays 514 for a third predetermined duration. Again, the delay isutilized so that the circuitry within the controller chip can processthe signals (i.e., conform to the control conditions). The thirdpredetermined delay can also vary widely with different implementations.For example, in one embodiment, the third predetermined delay is 1microsecond, which is the minimum time required before software clearsthe sleep state bit (e.g., the sleep state bit register 302). In anotherembodiment, the third predetermined delay can represent the timerequired for the hardware to unbypass the clocks, and then clear thesleep state bit.

After the third predetermined duration, the internal clocks are suppliedto the functional circuitry of the controller chip for normal operation.At this point the controller chip is powered-up and operable using theinternal clocks which are deemed stable. Hence, the power up processing500 is complete and ends. It should be noted that the first, second orthird predetermined delays can be implemented in software, hardware, ora combination of software and hardware.

FIG. 5B is a flow diagram of processing that results from the driving ofboth the I/O clock stop signal and the reset signal low in block 504 ofthe power up processing 500 shown in FIG. 5A. Although, in some cases,the processing operation is not needed because it is the existing stateor condition; nevertheless, for completeness and reliability reasons theprocessing is performed in any case.

Specifically, after the I/O clock stop signal and the reset signal aredriven 504 low, any input comparators within the clock generationcircuitry for the controller chip can be powered on 514. Inputcomparators are provided at the input of external clocks to thecontroller chip. Although not shown in FIG. 2A, the I/O controller chip202 could include one or more input comparators associated withreceiving the one or more input clocks at the I/O controller chip 202.Typically, the input comparators are used to compare the input clock toa common mode ground signal such that the common mode noise can beremoved from the input clock signal. The I/O controller chip 350 shownin FIG. 3B, for example, includes input comparators 352, 356 and 360.Next, the PLLs are powered off 516. The controller chip also has theability to separately control the supply of power to not only the inputcomparators but also the PLLs so as to better manage power consumption.The PLLs are then bypassed 518. As an example, the PLLs can be bypassedby selecting the bypass clock to pass through the multiplexers as theselected clock. For example, with respect to the I/O controller chip 202illustrated in FIG. 2A, the multiplexer 210 can select the bypass clockto be the selected clock and thus the run clock (normal clock) isbypassed.

Next, the sleep state bit is cleared 520. At this point, the bypassclock is supplied to the functional circuitry of the controller chip(e.g., I/O controller chip 202) as an internal clock. This allows thefunctional circuitry to be properly reset in accordance with the resetsignal (RESET) even though the actual operational clocks produced by thePLLs are not yet operable. In other words, during the initial stage ofthe power up of the controller chip, power is generally supplied to thecontroller chip but the PLLs and input comparators, if any, are not yetpowered on. Hence, in order to process the reset request (by the resetsignal in block 504), the controller chip makes use of a bypass clockthat is available during this initial stage of the power up. By usingthe bypass clock to provide the clocking for the reset request, thefunctional circuitry within the controller chip can be properly reset.Following block 520, the processing returns to the block 506 illustratedin FIG. 5A.

FIG. 5C is a flow diagram of processing that results from the driving ofthe reset signal high in block 508 of the power up processing 500 shownin FIG. 5A. Accordingly, during the delay 510 for the secondpredetermined duration, the processing shown in FIG. 5C is performed.Namely, the sleep state bit is set 522 and then the PLLs are powered on524. Once the sleep state bit is set 522, the internal clock (here, thebypass clock) is blocked from reaching the functional circuitry of thecontroller chip. Also, at this point, the reset request has been fullyprocessed so the use of the bypass clock is no longer needed. Then, thePLLs are powered on 524. Once powered, the PLLs start up and are allowedto stabilize with respect to the input clock (external clock) which isstable at this point.

FIG. 5D is a flow diagram of processing that results from the driving ofthe I/O clock stop signal high in block 512 of the power up processing500 shown in FIG. 5A. That is, after the I/O clock stop signal is drivenhigh, the processing shown in FIG. 5D is performed. Namely, thebypassing of the PLLs is removed 526. The bypassing 518 during theinitial stage is no longer needed and is therefore removed 526. At thispoint, the sleep state bit is set so that the selected clock is stoppedfrom being supplied to the functional circuitry of the controller chip.The third predetermined delay 514 provides time for a switchingoperation associated with removal 526 of the bypassing to be performed.

FIG. 5E is a flow diagram of processing that results after the thirdpredetermined delay 514 of FIG. 5A. Namely, the sleep state bit iscleared 528. At this point, the run clocks (normal clocks) produced bythe PLLs are stable and thus able to be reliably produced and providedby the clock generation circuitry to the functional circuitry asinternal clocks. As a result, by using this sequence of operations forthe power up processing 500, the internal clocks produced by PLLs thatare provided to functional circuitry within the same integrated circuitchip are guaranteed to be stable.

The I/O controller chip 202 besides having a powered-up mode and a shutdown mode, can also have a sleep mode in which some power saving isobtained for the I/O controller chip. In the sleep mode, the controllerchip remains generally powered but the clock generation circuitry islargely shutdown to conserve power.

FIG. 6 is a flow diagram of sleep processing 600 according to oneembodiment of the invention. The sleep processing 600 is, for example,performed by the I/O controller chip 202 when entering a sleep mode. Thesleep processing 600 initially drives 602 the I/O clock stop signal (I/OCLKSTOP) low. Next, there is a delay 604 for a predetermined duration sothat processing in response to the I/O clock stop signal being drivenlow can be performed. According to one embodiment, in response to theI/O clock stop signal being driven 602 low, the sleep state bit is set(which cleanly stops all clocks from being supplied to the functionalcircuitry), the power to the PLLs is then removed, and the power toinput comparators is also removed. Following the delay 604, the externalclocks supplied to the I/O controller chip 202 can be turned off 606.Following block 606, the sleep processing 600 is complete and ends.

Once the I/O controller chip 202 is placed in a sleep mode, it needs tobe awakened from the sleep mode to return to the run mode typically whenthere is activity that requires use of the functional circuitry of theI/O controller chip. The awakening of the I/O controller chip from thesleep mode can be performed by a particular sequence of operations.

FIG. 7 is a flow diagram of awaken processing 700 according to oneembodiment of the invention. The awaken processing 700 serves to returnthe I/O controller chip 202 from the sleep mode to the run mode.

The awaken processing 700 initially turns on 702 the external clocks.Then, the awaken processing 700 delays 704 for a predetermined duration(e.g., 10 milliseconds). During the predetermined duration, the externalclocks are stabilized. Next, the I/O clock stop signal is driven 706high. In response to the I/O clock stop signal being driven 706 high,the input comparators are powered on, and then the PLLs are powered on,while the sleep state bit remains set. The awaken processing 700 delays708 for a predetermined period (e.g., 250 microseconds) so that theprocessing responsive to the I/O stop signal being driven high can beperformed. Following the delay 708, the sleep state bit is cleared 710,which cleanly starts the clocks driving into the functional circuitry.At this point, the awaken processing 700 is complete and ends as theinternal clocks are now fully operational in a stable manner withrespect to the clocks produced by the PLLs.

Although the invention has been primarily described above with respectto the I/O controller chip, the invention is suited for use with anytype of controller chip or other functional chip that includes on-chipclock generation using PLLS. As examples, the controller chip or chipcan pertain to an I/O controller, an interrupt controller, a buscontroller, a microprocessor, an embedded controller, etc.

The invention can use a combination of hardware and software components.The software can be embodied as computer readable code on a computerreadable medium. The computer readable medium is any data storage devicethat can store data which can thereafter be read by a computer system.Examples of the computer readable medium include read-only memory,random-access memory, CD-ROMs, magnetic tape, optical data storagedevices. The computer readable medium can also be distributed over anetwork coupled computer system so that the computer readable code isstored and executed in a distributed fashion.

The advantages of the invention are numerous. Different embodiments orimplementations may have one or more of the following advantages. Oneadvantage of the invention is that stable clock generation with powermanagement can be performed internal to a functional integrated circuit.Another advantage of the invention is that functional integratedcircuits are able to be properly reset upon being initially powered-up.Yet another advantage of the invention is that phase-lock loops (PLLs)used in the clock generation lock to desired frequencies in a stablemanner. Still another advantage of the invention is that PLLs and clockscan be started and stopped cleanly and in the proper sequence, withouthaving to reset the logic associated with those clocks, for powermanagement.

The many features and advantages of the present invention are apparentfrom the written description and, thus, it is intended by the appendedclaims to cover all such features and advantages of the invention.Further, since numerous modifications and changes will readily occur tothose skilled in the art, it is not desired to limit the invention tothe exact construction and operation as illustrated and described.Hence, all suitable modifications and equivalents may be resorted to asfalling within the scope of the invention.

What is claimed is:
 1. An integrated circuit chip having internalfunctional circuitry, said integrated circuit chip receiving an externalclock, a reset signal and a clock stop signal, said integrated circuitchip comprising: a clock control circuit, said clock control circuitreceives the reset signal and the clock stop signal and produces a clockcontrol signal; a phase lock loop circuit, said phase lock loop receivesthe external clock and produces a generated clock based on the externalclock; a multiplexer operatively connected to said phase lock loopcircuit, said multiplexer receives the external clock and the generatedclock, and said multiplexer outputs at an output terminal one of theexternal clock and the generated clock as a selected clock based on theclock control signal; and a clock stopper operatively connected to theoutput terminal of said multiplexer, said clock stopper operates topermit or block passage of the selected clock to the internal functionalcircuitry of said integrated circuit chip.
 2. An integrated circuit chipas recited in claim 1, wherein said clock stopper operates to permit orblock passage of the selected clock to the internal functional circuitryof said integrated circuit chip based one at least one of the resetsignal and the clock stop signal.
 3. An integrated circuit chip asrecited in claim 2, wherein said integrated circuit is part of acomputer, and wherein said clock stopper is under control by softwarerunning on said computer.
 4. An integrated circuit chip as recited inclaim 1, wherein said integrated circuit chip is an Input/Output (I/O)controller chip.
 5. An integrated circuit chip as recited in claim 1,wherein said integrated circuit chip is an interrupt controller chip. 6.An integrated circuit chip as recited in claim 1, wherein saidintegrated circuit chip has a low power mode in which power isselectively removed from said phase lock loop circuit when the generatedclock is not needed.
 7. An integrated circuit chip as recited in claim1, wherein said clock stopper operates to cleanly permit or blockpassage of the selected clock to the internal functional circuitry ofsaid integrated circuit chip substantially without spikes or shortpulses.
 8. A functional integrated circuit chip for providing controlfunctions for a computer system, said functional integrated circuit chipcomprising: an on-board clock generation circuit that produces aplurality of clocks; and functional circuitry that operates using theplurality of clocks, wherein said on-board clock generation circuitincludes at least a clock control circuit, said clock control circuitreceives a reset signal and a clock stop signal and produces a clockcontrol signal; a phase lock loop circuit, said phase lock loop receivesan external clock and produces a generated clock based on the externalclock; a multiplexer operatively connected to said phase lock loopcircuit, said multiplexer receives the external clock and the generatedclock, and said multiplexer outputs at an output terminal one of theexternal clock and the generated clock as a selected clock based on theclock control signal; and a clock stopper operatively connected to theoutput terminal of said multiplexer, said clock stopper operates tocleanly permit or block passage of the selected clock to said functionalcircuitry of said functional integrated circuit chip.
 9. A functionalintegrated circuit chip as recited in claim 8, wherein said on-boardclock generation circuit has a run mode and a low-power mode, in the runmode the selected clock is supplied to said functional circuitry, and inthe low-power mode said clock stopper prevents the selected clock frombeing supplied to said functional circuitry.
 10. A functional integratedcircuit chip as recited in claim 9, wherein said on-board clockgeneration circuit further has a clock start-up mode, in the clockstart-up mode the selected clock is the external clock and is used toclock a reset through said functional integrated circuit chip.
 11. Afunctional integrated circuit chip as recited in claim 10, wherein saidfunctional integrated circuit chip is an input/output (I/O) controllerchip or an interrupt controller chip.
 12. A functional integratedcircuit as recited in claim 8, wherein said on-board clock generationcircuit further comprises: means for producing a bypass signal, andwherein said multiplexer outputs at the output terminal one of theexternal clock and the generated clock based on the bypass signal.
 13. Afunctional integrated circuit chip for providing control functions for acomputer system, said functional integrated circuit chip comprising: anon-board clock generation circuit that produces a plurality of clocks;and functional circuitry that operates using the plurality of clocks,wherein said on-board clock generation circuit includes at least a clockcontrol circuit, said clock control circuit receives a reset signal anda clock stop signal and produces a phase lock loop shutdown controlsignal; a phase lock loop circuit, said phase lock loop receives anexternal clock and produces a generated clock based on the externalclock; a clock stopper operatively connected to the output of said phaselock loop, said clock stopper operates to cleanly permit or blockpassage of either the external clock or the generated clock to saidfunctional circuitry of said functional integrated circuit chip, whereinsaid on-board clock generation circuit has a run mode and a low-powermode, in the run mode the generated clock is supplied to said functionalcircuitry, and in the low-power mode said clock stopper prevents eitherthe external clock or the generated clock from being supplied to saidfunctional circuitry, and wherein in the low-power mode, the phase lockloop shutdown control signal causes said phase lock loop circuit toshutdown said phase lock loop, thereby reducing power consumption.
 14. Afunctional integrated circuit chip as recited in claim 13, wherein thelow-power mode is a shutdown mode, and a reset operation associated witha power-up, following the shutdown mode, operates to supply the externalclock through said clock stopper to said functional circuitry so thatthe reset operation can be performed.
 15. A functional integratedcircuit chip as recited in claim 13, wherein said functional integratedcircuit chip is an input/output (I/O) controller chip or an interruptcontroller chip.
 16. A functional integrated circuit chip as recited inclaim 13, wherein when transitioning from the low-power mode to the runmode, said functional integrated circuit chip is reset and for a firstperiod of time during the transitioning the external clock passesthrough said clock stopper so that said functional circuitry can bereset, wherein after the first period of time during the transitioning,said phase lock loop circuit is powered-on, and wherein after a secondperiod of time following the powering-on of said phase lock loopcircuit, the generated clock is produced and stable and passes throughsaid clock stopper so as to achieve the run mode.
 17. A computer system,comprising: a memory device that stores computer code; a microprocessorchip that executes the computer code; a peripheral bus; and a chip forsaid peripheral bus, said chip comprising an on-board clock generationcircuit that produces a plurality of clocks, and functional circuitrythat operates using the plurality of clocks to control interaction withsaid peripheral bus, wherein said on-board clock generation circuitincludes at least a clock control circuit, said clock control circuitreceives a reset signal and a clock stop signal and produces a clockcontrol signal: a phase lock loop circuit, said phase lock loop receivesthe external clock and produces a generated clock based on an externalclock; a multiplexer operatively connected to said phase lock loopcircuit, said multiplexer receives the external clock and the generatedclock, and said multiplexer outputs at an output terminal one of theexternal clock and the generated clock as a selected clock based on theclock control signal; and a clock stopper operatively connected to theoutput terminal of said multiplexer, said clock stopper operates topermit or block passage of the selected clock to said functionalcircuitry of said chip.
 18. A functional integrated circuit chip asrecited in claim 17, wherein said on-board clock generation circuit hasa run mode and a low-power mode, in the run mode the selected clock issupplied to said functional circuitry, and in the low-power mode saidclock stopper prevents the selected clock from being supplied to saidfunctional circuitry.
 19. A functional integrated circuit chip asrecited in claim 18, wherein said on-board clock generation circuitfurther has a clock start-up mode, in the clock start-up mode theselected clock is the external clock and is used to clock a resetthrough said chip.
 20. A method for powering up an integrated circuitchip having functional circuitry and internal clock generation circuitryincluding phase-locked loops (PLLs) to produce internal clocks, saidmethod comprising: (a) providing power to the integrated circuit chipand to an external clock source but not providing power to the PLLs; (b)bypassing the PLLs to produce an externally generated clock, theexternally generated clock being provided by the external clock source;(c) permitting the externally generated clock to be supplied to thefunctional circuitry, thereby allowing processing of a reset operationwhile the PLLs are not producing the internal clocks; (d) subsequentlystopping the externally generated clock from being supplied to thefunctional circuitry after the reset operation is processed; (e)providing power to the PLLs; (f) unbypassing the PLLs; and (g)thereafter permitting the internal clocks produced by the PLLs to besupplied to the functional circuitry, so as to operate the functionalcircuitry in a normal manner.
 21. A method as recited in claim 20,wherein said stopping (d) is invoked after a first predetermined delayfollowing said permitting (c).
 22. A method as recited in claim 21,wherein said unbypassing (f) is invoked after a second predetermineddelay following said stopping (d).
 23. A method as recited in claim 22,wherein said permitting (g) is invoked after a third predetermined delayfollowing said unbypassing (f).
 24. A method as recited in claim 23,wherein the internal clocks produced by the PLLs and supplied to thefunctional circuitry are stabilized by said method.
 25. A method asrecited in claim 20, wherein the internal clocks produced by the PLLsand supplied to the functional circuitry are stabilized by said method.26. A method as recited in claim 20, wherein the integrated circuit chipis a chip including the functional circuitry and the internal clockgeneration circuitry.
 27. A method as recited in claim 20, wherein thechip is an I/O controller chip.